1. Field of the Invention
The invention especially relates to a video reproducing apparatus and a reproducing method for receiving and reproducing image data encoded by MPEG (Moving Picture Experts Group) 2 like a digital television broadcasting. More particularly, the invention relates to such video reproducing apparatus and method which can cope with a plurality of video signals whose frame frequencies are slightly different.
2. Description of the Related Art
A satellite digital television broadcasting for broadcasting a digital video signal by using a satellite has been started. The development of a ground wave digital television broadcasting for broadcasting a digital video signal by using a ground wave is also being progressed. In the digital television broadcasting, it is expected to perform various services such as high definition television broadcasting, multichannel broadcasting, multimedia broadcasting, and the like.
In the digital television broadcasting, for example, MPEG2 is used as an image compression system. According to the MPEG2 system, a video signal is compression encoded by a motion compensation predictive coding and a DCT (Discrete Cosine Transform). In the MPEG2 system, three kinds of picture planes called an I (Intra) picture, a P (Predicti) picture, and a B (Bidirectionally Predictive) picture are sent. In the I picture, a DCT encoding is performed by using pixels of the same frame. In the P picture, a DCT encoding using a motion compensation prediction is performed with reference to the I picture or P picture which has already been encoded. In the B picture, a DCT encoding using a motion prediction is performed with reference to the I pictures or P pictures before and after the target B picture.
A decoding circuit of MPEG2 is provided for a digital television receiver to receive a digital television broadcasting which is transmitted by using the MPEG2 system. The decoding circuit of MPEG2 can be constructed as shown in, for example, FIG. 1.
In FIG. 1, a bit stream of MPEG2 is supplied to an input terminal 101. The bit stream is once stored in a buffer memory 102.
An output of the buffer memory 102 is supplied to a variable length decoding circuit 103. A decoding is performed in the variable length decoding circuit 103 on a macroblock unit basis. Coefficient data of DCT and a motion vector are outputted from the variable length decoding circuit 103. Further, various control data indicative of a frame frequency of a video signal and data such as predictive mode, quantization scale, and the like are outputted from the variable length decoding circuit 103.
DCT coefficient data consisting of (8×8) pixels is supplied to an inverse quantizing circuit 104. A quantization scale of the inverse quantizing circuit 104 is set in accordance with quantization scale information from the variable length decoding circuit 103. Motion vector information and predictive mode information are supplied to a motion compensating circuit 107.
The DCT coefficient data is inversely quantized by the inverse quantizing circuit 104. An output of the inverse quantizing circuit 104 is supplied to an IDCT circuit 105. An output of the IDCT circuit 105 is supplied to an adding circuit 106. An output of the motion compensating circuit 107 is supplied to the adding circuit 106.
In the I picture, since the DCT encoding is performed by using pixels of the same frame, in case of the I picture, image data of a picture plane of one frame is derived from the IDCT circuit 105. The image data is outputted from an output terminal 111 via the adding circuit 106 and a buffer memory 110. The image data in this instance is stored as data of a reference picture plane into an image memory 108.
In the P picture, a DCT encoding using a motion compensation prediction is performed by referring to the I picture or P picture. Therefore, differential data between the relevant picture and the reference picture plane is outputted from the IDCT circuit 105. The data of the reference picture plane is stored in the image memory 108. A motion vector is supplied from the variable length decoding circuit 103 to the motion compensating circuit 107. In case of decoding the P picture, an image of a reference frame from the image memory 108 is motion compensated by the motion compensating circuit 107 and supplied to the adding circuit 106. In the adding circuit 106, the data of the motion compensated reference image and the differential data from the IDCT circuit 105 are added. Thus, data of the picture plane of one frame is derived. The image data is outputted from the output terminal 111 through the buffer memory 110. The image data in this instance is stored into the image memory 108 as data of the reference picture plane.
In the B picture, a DCT encoding using the motion prediction is performed by referring to the I pictures or P pictures before and after the target B picture. Therefore, differences between the target picture and the reference picture planes before and after it are outputted from the IDCT circuit 105. The data of the reference picture planes before and after the target picture is stored in the image memory 108. In case of decoding the B picture, the images of the reference frames before and after a target frame from the image memory 108 are motion compensated by the motion compensating circuit 107 and supplied to the adding circuit 106. In the adding circuit 106, the data of the motion compensated reference images before and after the target image and the differential data from the IDCT circuit 105 are added. Thus, the data of the picture plane of one frame is derived. The image data is outputted from the output terminal 111 via the buffer memory 110.
As mentioned above, the digital video signal of the MPEG2 system is decoded by the variable length decode circuit 103, inverse quantizing circuit 104, and IDCT circuit 105 and is outputted from the output terminal 111 via the buffer memory 110.
In the digital television broadcasting of the MPEG2 system, there is a possibility such that signals of a plurality of standards whose frame frequencies are slightly different are sent. Hitherto, therefore, it is necessary to prepare two clock generating circuits 121 and 122 for the buffer memory 110 and to switch the two clock generating circuits 121 and 122 in accordance with the frame frequency of the received television broadcasting.
That is, in a system mainly used as a standard to digitize the existing NTSC system, there is a standard in which the number of horizontal pixels of the video signal is set to 858 pixels, the number of scanning lines in one frame is set to 525 lines, and a clock frequency is set to 13.5 MHz. In this case, the frame frequency is obtained by13.5 MHz/(858×525)and its value is equal to 29.97 Hz.
On the other hand, as a standard of a digital NTSC system which will be newly standardized in future, there is a standard such that a horizontal frequency of the video signal is set to 858 pixels, the number of scanning lines in one frame is set to 525 lines, and a clock frequency is set to 13.5 MHz. According to this standard, the frame frequency is equal to just 30 Hz.
As mentioned above, in the digital television broadcasting of the MPEG2 system, there are the standard having the frame frequency of 29.97 Hz and the standard having the frame frequency of 30 Hz. Therefore, while the digital television broadcasting having the frame frequency of 29.97 Hz is being received, it is necessary to control the reading operation from the buffer memory 110 so as to set the frame frequency to 29.97 Hz. While the digital television broadcasting having the frame frequency of 30 Hz is being received, it is necessary to control the reading operation from the buffer memory 110 so as to set the frame frequency to 30 Hz.
For this purpose, hitherto, two clock generating circuits 121 and 122 are provided and the two clock generating circuits 121 and 122 are switched in accordance with the frame frequency of the received video signal.
That is, in FIG. 1, an output of the clock generating circuit 121 is supplied to a terminal 123A of a switching circuit 123. An output of the clock generating circuit 122 is supplied to a terminal 123B of the switching circuit 123. The clock generating circuit 121 generates a clock to the buffer memory 110 so that the video data is read out at a frame frequency 29.97 Hz. The clock generating circuit 122 generates a clock to the buffer memory 110 so that the video data is read out at a frame frequency 30 Hz. The clock generating circuits 121 and 122 generate the clocks on the basis of a system clock from a system clock generating circuit 120. An output of the switching circuit 123 is supplied to the buffer circuit 110.
Various control data showing the frame frequencies of the video signals are included in the output of the variable length decoding circuit 103. The control data is supplied to a frame frequency decoder 124. In the frame frequency decoder 124, the frame frequency of the received video signal is discriminated and a switch change-over signal is generated from the frame frequency decoder 124 in accordance with the frame frequency. When the received video signal has the frame frequency of 29.97 Hz, the switching circuit 123 is set to the terminal 123A side. Therefore, the video data is read out from the buffer memory 110 at the frame frequency of 29.97 Hz.
When the received video signal has the frame frequency of 30 Hz, the switching circuit 123 is set to the terminal 123B side. Therefore, the video data is read out from the buffer memory 110 at the frame frequency 30 Hz.
As mentioned above, in the digital television broadcasting, since there is a possibility such that a plurality of video signals whose frame frequencies are slightly different are transmitted, hitherto, it is necessary to prepare a plurality of clock generating circuits 121 and 122 corresponding to the frame frequencies.
Although it is also considered to, for example, generate clocks of two frame frequencies from one oscillating circuit, as mentioned above, the necessary frame frequencies are very close frequencies such as 29.97 Hz and 30 Hz. A ratio of those two frequencies is equal to (1000/1001). It is very difficult to stably generate the clocks corresponding to two frequencies from one oscillating circuit.
As mentioned above, if a plurality of clock generating circuits are prepared in accordance with the frame frequencies of the video signals which are received, a problem that a circuit scale increases and the costs rise occurs. When the digital television receiver is realized as an integrated circuit, particularly, it is difficult to mount the clock generating circuit including the oscillating circuit onto the same chip as that of the decoding circuit. Therefore, if a plurality of clock generating circuits are provided, the circuit scale is increased and the costs are raised.